From 7ddb0ab85f04f56371ae948052188d968725b8b7 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Mon, 14 Jul 2014 13:08:14 +0000 Subject: [mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938 --- llvm/lib/Target/Mips/MipsMachineFunction.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'llvm/lib/Target/Mips/MipsMachineFunction.cpp') diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index a3306686fc4..bc896be4e1d 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -137,12 +137,12 @@ MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *Val) { return MachinePointerInfo(E); } -int MipsFunctionInfo::getBuildPairF64_FI(const TargetRegisterClass *RC) { - if (BuildPairF64_FI == -1) { - BuildPairF64_FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), - RC->getAlignment(), false); +int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { + if (MoveF64ViaSpillFI == -1) { + MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject( + RC->getSize(), RC->getAlignment(), false); } - return BuildPairF64_FI; + return MoveF64ViaSpillFI; } void MipsFunctionInfo::anchor() { } -- cgit v1.2.3