From 50f17235dd45e7023dda46cba0ea15ce1ef3f6f0 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 15 Sep 2015 16:17:27 +0000 Subject: Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702 --- llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp') diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 13f90d434a3..328e71720ca 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -411,31 +411,27 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, // MCAsmBackend MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); } MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ true); } -- cgit v1.2.3