From 51a7ae2a2936dd686115950871cb599cf47cf089 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Thu, 5 Oct 2017 10:27:37 +0000 Subject: [mips] Place certain 64 bit FPU instructions in their own decoder namespace Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976 --- llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target/Mips/Disassembler') diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 15195564301..002fa512b21 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1283,9 +1283,9 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, return Result; } - if (hasMips32r6() && isFP64()) { - DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, + if (isFP64()) { + DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -1368,6 +1368,14 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, return Result; } + if (isFP64()) { + DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. Result = -- cgit v1.2.3