From 84e4d59e47542e633fc2167c5996cf1ad484ef15 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Tue, 17 May 2016 11:10:15 +0000 Subject: [mips][microMIPS] Implement BEQZC and BNEZC instructions Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755 --- llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 5f1cf894ed0..5dfe37f1cff 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -209,6 +209,11 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, + unsigned Offset, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, @@ -1861,6 +1866,16 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, + unsigned Offset, + uint64_t Address, + const void *Decoder) { + int32_t BranchOffset = SignExtend32<21>(Offset) << 1; + + Inst.addOperand(MCOperand::createImm(BranchOffset)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, -- cgit v1.2.3