From 55e446737feb6c0b0a15ae95c0b489796658d0db Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Thu, 14 Sep 2017 17:27:53 +0000 Subject: [mips] Implement the 'dext' aliases and it's disassembly alias. The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276 --- .../Target/Mips/Disassembler/MipsDisassembler.cpp | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 8bd2e791998..ac92fdb6f9e 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -523,6 +523,10 @@ template static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -1055,6 +1059,60 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, return MCDisassembler::Success; } +// Override the generated disassembler to produce DEXT all the time. This is +// for feature / behaviour parity with binutils. +template +static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, + const void *Decoder) { + unsigned Msbd = fieldFromInstruction(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + bool IsMicroMips = false; + + switch (MI.getOpcode()) { + case Mips::DEXT_MM64R6: + IsMicroMips = true; + LLVM_FALLTHROUGH; + case Mips::DEXT: + Pos = Lsb; + Size = Msbd + 1; + break; + case Mips::DEXTM_MM64R6: + IsMicroMips = true; + LLVM_FALLTHROUGH; + case Mips::DEXTM: + Pos = Lsb; + Size = Msbd + 1 + 32; + break; + case Mips::DEXTU_MM64R6: + IsMicroMips = true; + LLVM_FALLTHROUGH; + case Mips::DEXTU: + Pos = Lsb + 32; + Size = Msbd + 1; + break; + default: + llvm_unreachable("Unknown DEXT instruction!"); + } + + MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT); + + // Although the format of the instruction is similar, rs and rt are swapped + // for microMIPS64R6. + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + if (IsMicroMips) + std::swap(Rs, Rt); + + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); + MI.addOperand(MCOperand::createImm(Pos)); + MI.addOperand(MCOperand::createImm(Size)); + + return MCDisassembler::Success; +} + // Override the generated disassembler to produce DINS all the time. This is // for feature / behaviour parity with binutils. template -- cgit v1.2.3