From e473dc937f59a9fefe450725ca4774a5245826a2 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Mon, 9 May 2016 13:38:25 +0000 Subject: [mips][micromips] Make getPointerRegClass() result depend on the instruction. Summary: Previously, it returned the GPR16MMRegClass for all instructions which was incorrect for instructions like lwsp/lwgp and unnecesarily restricted the permitted registers for instructions like lw32. This fixes quite a few of the -verify-machineinstrs errors reported in PR27458. I've only added -verify-machineinstrs to one test in this change since I understand there is a plan to enable the verifier by default. Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19873 llvm-svn: 268918 --- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp') diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index bff46886dc7..02922bccccf 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1092,6 +1092,11 @@ public: && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP); } + template bool isMemWithSimmWordAlignedOffsetGP() const { + return isMem() && isConstantMemOff() && isInt(getConstantMemOff()) + && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() + && (getMemBase()->getGPR32Reg() == Mips::GP); + } template bool isScaledUImm() const { return isConstantImm() && -- cgit v1.2.3