From 9e3e4a9219dcb07ecbf0897cbd9d9b39d1cd9630 Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Mon, 26 Jan 2009 03:31:40 +0000 Subject: CellSPU: - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen. llvm-svn: 62990 --- llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target/CellSPU/SPUInstrInfo.cpp') diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index 91d52facada..f35a42d71a9 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -155,13 +155,13 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, case SPU::ORr8_r32: case SPU::ORr32_r16: case SPU::ORr32_r8: - case SPU::ORr32_r64: case SPU::ORr16_r64: case SPU::ORr8_r64: - case SPU::ORr64_r32: case SPU::ORr64_r16: case SPU::ORr64_r8: */ + case SPU::ORr64_r32: + case SPU::ORr32_r64: case SPU::ORf32_r32: case SPU::ORr32_f32: case SPU::ORf64_r64: -- cgit v1.2.3