From 635f2a69d997b676d1a277665544faba4e231cd1 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Fri, 13 Feb 2009 02:30:42 +0000 Subject: Remove non-DebugLoc versions of BuildMI from Alpha and Cell. llvm-svn: 64433 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 21 +++++++++--------- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 14 ++++++------ llvm/lib/Target/Alpha/AlphaLLRP.cpp | 21 +++++++++--------- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 33 ++++++++++++++++------------- 4 files changed, 48 insertions(+), 41 deletions(-) (limited to 'llvm/lib/Target/Alpha') diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index e4d3ecdff9a..10011125cf8 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -728,6 +728,7 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, //test sc and maybe branck to start //exit: const BasicBlock *LLVM_BB = BB->getBasicBlock(); + DebugLoc dl = MI->getDebugLoc(); MachineFunction::iterator It = BB; ++It; @@ -741,46 +742,46 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, F->insert(It, llscMBB); F->insert(It, sinkMBB); - BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB); + BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB); unsigned reg_res = MI->getOperand(0).getReg(), reg_ptr = MI->getOperand(1).getReg(), reg_v2 = MI->getOperand(2).getReg(), reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass); - BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), + BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), reg_res).addImm(0).addReg(reg_ptr); switch (MI->getOpcode()) { case Alpha::CAS32: case Alpha::CAS64: { unsigned reg_cmp = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass); - BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp) + BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp) .addReg(reg_v2).addReg(reg_res); - BuildMI(llscMBB, TII->get(Alpha::BEQ)) + BuildMI(llscMBB, dl, TII->get(Alpha::BEQ)) .addImm(0).addReg(reg_cmp).addMBB(sinkMBB); - BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store) + BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store) .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg()); break; } case Alpha::LAS32: case Alpha::LAS64: { - BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store) + BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store) .addReg(reg_res).addReg(reg_v2); break; } case Alpha::SWAP32: case Alpha::SWAP64: { - BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store) + BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store) .addReg(reg_v2).addReg(reg_v2); break; } } - BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store) + BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store) .addReg(reg_store).addImm(0).addReg(reg_ptr); - BuildMI(llscMBB, TII->get(Alpha::BEQ)) + BuildMI(llscMBB, dl, TII->get(Alpha::BEQ)) .addImm(0).addReg(reg_store).addMBB(llscMBB); - BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB); + BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB); thisMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(llscMBB); diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp index 42dc4480212..73e9b7b2d57 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -108,6 +108,8 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "Alpha branch conditions have two components!"); @@ -115,25 +117,25 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB); return 2; } diff --git a/llvm/lib/Target/Alpha/AlphaLLRP.cpp b/llvm/lib/Target/Alpha/AlphaLLRP.cpp index 7a1b78497b8..0c51bc554be 100644 --- a/llvm/lib/Target/Alpha/AlphaLLRP.cpp +++ b/llvm/lib/Target/Alpha/AlphaLLRP.cpp @@ -49,6 +49,7 @@ namespace { const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; + DebugLoc dl = DebugLoc::getUnknownLoc(); unsigned count = 0; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { @@ -73,7 +74,7 @@ namespace { prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; @@ -85,10 +86,10 @@ namespace { MI->getOperand(1).getImm()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; @@ -99,12 +100,12 @@ namespace { && prev[2]->getOperand(1).getImm() == MI->getOperand(1).getImm()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; } @@ -136,7 +137,7 @@ namespace { if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index a0b6e09c50a..2ed8dac16a1 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -202,20 +202,21 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); static int curgpdist = 0; //handle GOP offset - BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) .addGlobalAddress(const_cast(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo @@ -236,13 +237,13 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { // adjust stack pointer: r30 -= numbytes NumBytes = -NumBytes; if (NumBytes >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes)) - .addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes)) - .addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { cerr << "Too big a stack frame at " << NumBytes << "\n"; abort(); @@ -251,10 +252,10 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, TII.get(Alpha::STQ)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) .addReg(Alpha::R30).addReg(Alpha::R30); } @@ -267,6 +268,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, assert((MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp) && "Can only insert epilog into returning blocks"); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); @@ -276,20 +278,21 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, //now if we need to, restore the old FP if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) .addReg(Alpha::R15); //restore the FP - BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) + .addImm(0).addReg(Alpha::R15); } if (NumBytes != 0) { if (NumBytes <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { cerr << "Too big a stack frame at " << NumBytes << "\n"; -- cgit v1.2.3