From dfbf91e59d20b27bf7aaa411f92d07369722c009 Mon Sep 17 00:00:00 2001
From: Andrew Lenharth <andrewl@lenharth.org>
Date: Tue, 31 Oct 2006 23:46:56 +0000
Subject: more shotenning

llvm-svn: 31331
---
 llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'llvm/lib/Target/Alpha/AlphaInstrInfo.cpp')

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 90ef7bbaac6..7a342b96430 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == Alpha::BIS    || 
+  if (oc == Alpha::BISr   || 
       oc == Alpha::CPYSS  || 
       oc == Alpha::CPYST  ||
       oc == Alpha::CPYSSt || 
@@ -229,7 +229,7 @@ void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 
 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, 
                                 MachineBasicBlock::iterator MI) const {
-  BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+  BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
     .addReg(Alpha::R31);
 }
 
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