From f520093eb3f796e90e6a7ca01a50afe44bc09764 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sun, 25 Dec 2005 17:36:48 +0000 Subject: add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG llvm-svn: 25011 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp') diff --git a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp index 59b9199b920..29627c518d9 100644 --- a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp +++ b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp @@ -136,9 +136,9 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { case MachineOperand::MO_GlobalAddress: //Abuse PCrel to specify pcrel calls //calls are the only thing that use this flag - if (MO.isPCRelative()) - O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng"; - else +// if (MO.isPCRelative()) +// O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng"; +// else O << Mang->getValueName(MO.getGlobal()); return; -- cgit v1.2.3