From 774b441b5e11a92d179f57a90c277b48ec74c802 Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Tue, 24 Mar 2015 09:17:25 +0000 Subject: Use std::bitset for SubtargetFeatures Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055 --- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMSubtarget.cpp | 4 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 156 +++++++++++---------- .../Target/ARM/Disassembler/ARMDisassembler.cpp | 71 +++++----- llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 14 +- llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h | 2 +- .../Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 4 +- .../Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 8 +- 9 files changed, 136 insertions(+), 127 deletions(-) (limited to 'llvm/lib/Target/ARM') diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 971e10df8b9..e21135c7cd3 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -420,7 +420,7 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, } static bool isThumb(const MCSubtargetInfo& STI) { - return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + return STI.getFeatureBits()[ARM::ModeThumb]; } void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 7ee3cb0a3d1..1dfc6194406 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -4513,7 +4513,7 @@ breakPartialRegDependency(MachineBasicBlock::iterator MI, } bool ARMBaseInstrInfo::hasNOP() const { - return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0; + return Subtarget.getFeatureBits()[ARM::HasV6KOps]; } bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 3b0d787528d..a994869267e 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -263,8 +263,8 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { } // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default. - uint64_t Bits = getFeatureBits(); - if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters + const FeatureBitset &Bits = getFeatureBits(); + if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters (Options.UnsafeFPMath || isTargetDarwin())) UseNEONForSinglePrecisionFP = true; } diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index f7d397b7f02..61dde57015c 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -244,37 +244,37 @@ class ARMAsmParser : public MCTargetAsmParser { bool isThumb() const { // FIXME: Can tablegen auto-generate this? - return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + return STI.getFeatureBits()[ARM::ModeThumb]; } bool isThumbOne() const { - return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; + return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2]; } bool isThumbTwo() const { - return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); + return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2]; } bool hasThumb() const { - return STI.getFeatureBits() & ARM::HasV4TOps; + return STI.getFeatureBits()[ARM::HasV4TOps]; } bool hasV6Ops() const { - return STI.getFeatureBits() & ARM::HasV6Ops; + return STI.getFeatureBits()[ARM::HasV6Ops]; } bool hasV6MOps() const { - return STI.getFeatureBits() & ARM::HasV6MOps; + return STI.getFeatureBits()[ARM::HasV6MOps]; } bool hasV7Ops() const { - return STI.getFeatureBits() & ARM::HasV7Ops; + return STI.getFeatureBits()[ARM::HasV7Ops]; } bool hasV8Ops() const { - return STI.getFeatureBits() & ARM::HasV8Ops; + return STI.getFeatureBits()[ARM::HasV8Ops]; } bool hasARM() const { - return !(STI.getFeatureBits() & ARM::FeatureNoARM); + return !STI.getFeatureBits()[ARM::FeatureNoARM]; } bool hasThumb2DSP() const { - return STI.getFeatureBits() & ARM::FeatureDSPThumb2; + return STI.getFeatureBits()[ARM::FeatureDSPThumb2]; } bool hasD16() const { - return STI.getFeatureBits() & ARM::FeatureD16; + return STI.getFeatureBits()[ARM::FeatureD16]; } void SwitchMode() { @@ -282,7 +282,7 @@ class ARMAsmParser : public MCTargetAsmParser { setAvailableFeatures(FB); } bool isMClass() const { - return STI.getFeatureBits() & ARM::FeatureMClass; + return STI.getFeatureBits()[ARM::FeatureMClass]; } /// @name Auto-generated Match Functions @@ -9186,52 +9186,53 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { // tools/clang/lib/Driver/Tools.cpp static const struct { const unsigned ID; - const uint64_t Enabled; - const uint64_t Disabled; + const FeatureBitset Enabled; + const FeatureBitset Disabled; } FPUs[] = { - {/* ID */ ARM::VFP, - /* Enabled */ ARM::FeatureVFP2, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::VFPV2, - /* Enabled */ ARM::FeatureVFP2, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::VFPV3, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16}, - {/* ID */ ARM::VFPV3_D16, - /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::VFPV4, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16}, - {/* ID */ ARM::VFPV4_D16, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureD16, - /* Disabled */ ARM::FeatureNEON}, - {/* ID */ ARM::FPV5_D16, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8 | ARM::FeatureD16, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto}, - {/* ID */ ARM::FP_ARMV8, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8, - /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16}, - {/* ID */ ARM::NEON, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON, - /* Disabled */ ARM::FeatureD16}, - {/* ID */ ARM::NEON_VFPV4, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureNEON, - /* Disabled */ ARM::FeatureD16}, - {/* ID */ ARM::NEON_FP_ARMV8, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8 | ARM::FeatureNEON, - /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16}, - {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8, - /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | - ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, - /* Disabled */ ARM::FeatureD16}, - {ARM::SOFTVFP, 0, 0}, + {/* ID */ ARM::VFP, + /* Enabled */ {ARM::FeatureVFP2}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::VFPV2, + /* Enabled */ {ARM::FeatureVFP2}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::VFPV3, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}}, + {/* ID */ ARM::VFPV3_D16, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureD16}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::VFPV4, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}}, + {/* ID */ ARM::VFPV4_D16, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureD16}, + /* Disabled */ {ARM::FeatureNEON}}, + {/* ID */ ARM::FPV5_D16, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8, ARM::FeatureD16}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}}, + {/* ID */ ARM::FP_ARMV8, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8}, + /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto, ARM::FeatureD16}}, + {/* ID */ ARM::NEON, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON}, + /* Disabled */ {ARM::FeatureD16}}, + {/* ID */ ARM::NEON_VFPV4, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureNEON}, + /* Disabled */ {ARM::FeatureD16}}, + {/* ID */ ARM::NEON_FP_ARMV8, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8, ARM::FeatureNEON}, + /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}}, + {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8, + /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4, + ARM::FeatureFPARMv8, ARM::FeatureNEON, + ARM::FeatureCrypto}, + /* Disabled */ {ARM::FeatureD16}}, + {ARM::SOFTVFP, {}, {}}, }; /// parseDirectiveFPU @@ -9256,8 +9257,8 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { // Need to toggle features that should be on but are off and that // should off but are on. - uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) | - (Entry.Disabled & STI.getFeatureBits()); + FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) | + (Entry.Disabled & STI.getFeatureBits()); setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle))); break; } @@ -9994,30 +9995,30 @@ extern "C" void LLVMInitializeARMAsmParser() { static const struct { const char *Name; const unsigned ArchCheck; - const uint64_t Features; + const FeatureBitset Features; } Extensions[] = { - { "crc", Feature_HasV8, ARM::FeatureCRC }, + { "crc", Feature_HasV8, {ARM::FeatureCRC} }, { "crypto", Feature_HasV8, - ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 }, - { "fp", Feature_HasV8, ARM::FeatureFPARMv8 }, + {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} }, + { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} }, { "idiv", Feature_HasV7 | Feature_IsNotMClass, - ARM::FeatureHWDiv | ARM::FeatureHWDivARM }, + {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} }, // FIXME: iWMMXT not supported - { "iwmmxt", Feature_None, 0 }, + { "iwmmxt", Feature_None, {} }, // FIXME: iWMMXT2 not supported - { "iwmmxt2", Feature_None, 0 }, + { "iwmmxt2", Feature_None, {} }, // FIXME: Maverick not supported - { "maverick", Feature_None, 0 }, - { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP }, + { "maverick", Feature_None, {} }, + { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} }, // FIXME: ARMv6-m OS Extensions feature not checked - { "os", Feature_None, 0 }, + { "os", Feature_None, {} }, // FIXME: Also available in ARMv6-K - { "sec", Feature_HasV7, ARM::FeatureTrustZone }, - { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 }, + { "sec", Feature_HasV7, {ARM::FeatureTrustZone} }, + { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} }, // FIXME: Only available in A-class, isel not predicated - { "virt", Feature_HasV7, ARM::FeatureVirtualization }, + { "virt", Feature_HasV7, {ARM::FeatureVirtualization} }, // FIXME: xscale not supported - { "xscale", Feature_None, 0 }, + { "xscale", Feature_None, {} }, }; /// parseDirectiveArchExtension @@ -10045,7 +10046,7 @@ bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { if (Extension.Name != Name) continue; - if (!Extension.Features) + if (Extension.Features.none()) report_fatal_error("unsupported architectural extension: " + Name); if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) { @@ -10054,9 +10055,10 @@ bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { return false; } - uint64_t ToggleFeatures = EnableFeature - ? (~STI.getFeatureBits() & Extension.Features) - : ( STI.getFeatureBits() & Extension.Features); + FeatureBitset ToggleFeatures = EnableFeature + ? (~STI.getFeatureBits() & Extension.Features) + : ( STI.getFeatureBits() & Extension.Features); + uint64_t Features = ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); setAvailableFeatures(Features); diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 4d5122a7620..bd04422f67f 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -431,7 +431,7 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, raw_ostream &CS) const { CommentStream = &CS; - assert(!(STI.getFeatureBits() & ARM::ModeThumb) && + assert(!STI.getFeatureBits()[ARM::ModeThumb] && "Asked to disassemble an ARM instruction but Subtarget is in Thumb " "mode!"); @@ -696,7 +696,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, raw_ostream &CS) const { CommentStream = &CS; - assert((STI.getFeatureBits() & ARM::ModeThumb) && + assert(STI.getFeatureBits()[ARM::ModeThumb] && "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); // We want to read exactly 2 bytes of data. @@ -1022,9 +1022,10 @@ static const uint16_t DPRDecoderTable[] = { static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasD16 = featureBits & ARM::FeatureD16; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasD16 = featureBits[ARM::FeatureD16]; if (RegNo > 31 || (hasD16 && RegNo > 15)) return MCDisassembler::Fail; @@ -1369,9 +1370,9 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, break; } - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + if (featureBits[ARM::HasV8Ops] && (coproc != 14)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(coproc)); @@ -3267,10 +3268,11 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = featureBits & ARM::FeatureMP; - bool hasV7Ops = featureBits & ARM::HasV7Ops; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3353,10 +3355,11 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, imm |= (Rn << 9); unsigned add = fieldFromInstruction(Insn, 9, 1); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = featureBits & ARM::FeatureMP; - bool hasV7Ops = featureBits & ARM::HasV7Ops; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3433,10 +3436,11 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, unsigned imm = fieldFromInstruction(Insn, 0, 12); imm |= (Rn << 13); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = (featureBits & ARM::FeatureMP); - bool hasV7Ops = (featureBits & ARM::HasV7Ops); + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3550,9 +3554,10 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, unsigned U = fieldFromInstruction(Insn, 23, 1); int imm = fieldFromInstruction(Insn, 0, 12); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasV7Ops = (featureBits & ARM::HasV7Ops); + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rt == 15) { switch (Inst.getOpcode()) { @@ -3873,9 +3878,10 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, if (Val == 0xA || Val == 0xB) return MCDisassembler::Fail; - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(Val)); @@ -4025,9 +4031,10 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if (FeatureBits & ARM::FeatureMClass) { + const FeatureBitset &FeatureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if (FeatureBits[ARM::FeatureMClass]) { unsigned ValLow = Val & 0xff; // Validate the SYSm value first. @@ -4047,7 +4054,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, case 17: // basepri case 18: // basepri_max case 19: // faultmask - if (!(FeatureBits & ARM::HasV7Ops)) + if (!(FeatureBits[ARM::HasV7Ops])) // Values basepri, basepri_max and faultmask are only valid for v7m. return MCDisassembler::Fail; break; @@ -4057,7 +4064,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, if (Inst.getOpcode() == ARM::t2MSR_M) { unsigned Mask = fieldFromInstruction(Val, 10, 2); - if (!(FeatureBits & ARM::HasV7Ops)) { + if (!(FeatureBits[ARM::HasV7Ops])) { // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are // unpredictable. if (Mask != 2) @@ -4071,7 +4078,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, // indicates the move for the GE{3:0} bits, the mask{0} bit can be set // only if the processor includes the DSP extension. if (Mask == 0 || (Mask != 2 && ValLow > 3) || - (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) + (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1))) S = MCDisassembler::SoftFail; } } diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 16eea335261..41287df8276 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -90,7 +90,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, case 3: O << "\twfi"; break; case 4: O << "\tsev"; break; case 5: - if ((getAvailableFeatures() & ARM::HasV8Ops)) { + if (getAvailableFeatures()[ARM::HasV8Ops]) { O << "\tsevl"; break; } // Fallthrough for non-v8 @@ -299,7 +299,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() && MI->getOperand(0).getImm() == 0 && - (getAvailableFeatures() & ARM::FeatureVirtualization)) { + getAvailableFeatures()[ARM::FeatureVirtualization]) { O << "\teret"; printPredicateOperand(MI, 1, O); printAnnotation(O, Annot); @@ -698,7 +698,7 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops)); + O << ARM_MB::MemBOptToString(val, getAvailableFeatures()[ARM::HasV8Ops]); } void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, @@ -796,14 +796,14 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCOperand &Op = MI->getOperand(OpNum); unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; - uint64_t FeatureBits = getAvailableFeatures(); + const FeatureBitset &FeatureBits = getAvailableFeatures(); - if (FeatureBits & ARM::FeatureMClass) { + if (FeatureBits[ARM::FeatureMClass]) { unsigned SYSm = Op.getImm(); unsigned Opcode = MI->getOpcode(); // For writes, handle extended mask bits if the DSP extension is present. - if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) { + if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) { switch (SYSm) { case 0x400: O << "apsr_g"; return; case 0xc00: O << "apsr_nzcvqg"; return; @@ -819,7 +819,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, // Handle the basic 8-bit mask. SYSm &= 0xff; - if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) { + if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { // ARMv7-M deprecates using MSR APSR without a _ qualifier as an // alias for MSR APSR_nzcvq. switch (SYSm) { diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index f4f10821037..1246cc46a60 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -33,7 +33,7 @@ public: return ARM::NumTargetFixupKinds; } - bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; } + bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index e48cabbf7ee..4d1bec33401 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -51,10 +51,10 @@ public: ~ARMMCCodeEmitter() {} bool isThumb(const MCSubtargetInfo &STI) const { - return (STI.getFeatureBits() & ARM::ModeThumb) != 0; + return STI.getFeatureBits()[ARM::ModeThumb]; } bool isThumb2(const MCSubtargetInfo &STI) const { - return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; + return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; } bool isTargetMachO(const MCSubtargetInfo &STI) const { Triple TT(STI.getTargetTriple()); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 82dac5c4357..3ecd559348a 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -33,7 +33,7 @@ using namespace llvm; static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - if (STI.getFeatureBits() & llvm::ARM::HasV7Ops && + if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && // Checks for the deprecated CP15ISB encoding: @@ -65,7 +65,7 @@ static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() && + if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) { Info = "applying IT instruction to more than one subsequent instruction is " "deprecated"; @@ -77,7 +77,7 @@ static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) && + assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && "cannot predicate thumb instructions"); assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); @@ -94,7 +94,7 @@ static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) { - assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) && + assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && "cannot predicate thumb instructions"); assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); -- cgit v1.2.3