From c3b931d0050a44e4ef14a9cc3f5fd0684307cb60 Mon Sep 17 00:00:00 2001 From: Bradley Smith Date: Mon, 19 May 2014 15:58:15 +0000 Subject: [ARM64] Split tbz/tbnz into W/X register variant llvm-svn: 209134 --- llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp') diff --git a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp index d14e3a86f8f..92eabcf2b4e 100644 --- a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp +++ b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp @@ -1512,7 +1512,10 @@ static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, if (dst & (1 << (14 - 1))) dst |= ~((1LL << 14) - 1); - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + if (fieldFromInstruction(insn, 31, 1) == 0) + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + else + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); Inst.addOperand(MCOperand::CreateImm(bit)); if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) Inst.addOperand(MCOperand::CreateImm(dst)); -- cgit v1.2.3