From 0910b5afacf35704c854f103b7ecca03e3e11f28 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Wed, 17 Mar 2010 23:14:23 +0000 Subject: Fixed a bug in the IT mask printing where T means the cond bit in the mask matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also tagged in the Mask to facilitate Asm printing. The disassembler also depends on this arrangement. This is similar to what's described in A2.5.2 ITSTATE. Ran: utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2 successfully. llvm-svn: 98775 --- llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp') diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index f5ba155f402..f36d4ef7567 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -78,14 +78,16 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) { DebugLoc ndl = NMI->getDebugLoc(); unsigned NPredReg = 0; ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg); - if (NCC == OCC) { - Mask |= (1 << Pos); - } else if (NCC != CC) + if (NCC == CC || NCC == OCC) + Mask |= (NCC & 1) << Pos; + else break; --Pos; ++MBBI; } Mask |= (1 << Pos); + // Tag along (firstcond[0] << 4) with the mask. + Mask |= (CC & 1) << 4; MIB.addImm(Mask); Modified = true; ++NumITs; -- cgit v1.2.3