From 9ca33e8a9fd35a0ef0ea99e3a31ba280e38ec630 Mon Sep 17 00:00:00 2001 From: David Goodwin Date: Wed, 8 Jul 2009 18:31:39 +0000 Subject: Push methods into base class in preparation for sharing. llvm-svn: 75020 --- llvm/lib/Target/ARM/Thumb1RegisterInfo.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'llvm/lib/Target/ARM/Thumb1RegisterInfo.h') diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.h b/llvm/lib/Target/ARM/Thumb1RegisterInfo.h index 6d4f1f0bf5e..28a5046659b 100644 --- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.h +++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.h @@ -20,27 +20,26 @@ namespace llvm { class ARMSubtarget; - class TargetInstrInfo; + class ARMBaseInstrInfo; class Type; struct Thumb1RegisterInfo : public ARMBaseRegisterInfo { public: - Thumb1RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI); + Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI); /// emitLoadConstPool - Emits a load from constpool to materialize the /// specified immediate. - void emitLoadConstPool(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, int Val, - const TargetInstrInfo *TII, - DebugLoc dl) const; + void emitLoadConstPool(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + const TargetInstrInfo *TII, DebugLoc dl, + unsigned DestReg, int Val, + ARMCC::CondCodes Pred = ARMCC::AL, + unsigned PredReg = 0) const; /// Code Generation virtual methods... const TargetRegisterClass * getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; - bool isReservedReg(const MachineFunction &MF, unsigned Reg) const; - bool requiresRegisterScavenging(const MachineFunction &MF) const; bool hasReservedCallFrame(MachineFunction &MF) const; -- cgit v1.2.3