From 947f04bad0eddbb214aa31f34e7e4af1cc3ac109 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Sat, 13 Mar 2010 01:08:20 +0000 Subject: Change ARM ld/st multiple instructions to have variant instructions for writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409 --- llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 2 -- 1 file changed, 2 deletions(-) (limited to 'llvm/lib/Target/ARM/Thumb1InstrInfo.cpp') diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp index 7f42c82abe9..29ae631269a 100644 --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -159,7 +159,6 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); AddDefaultPred(MIB); - MIB.addReg(0); // No write back. for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); // Add the callee-saved register as live-in. It's killed at the spill. @@ -182,7 +181,6 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, DebugLoc DL = MI->getDebugLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); AddDefaultPred(MIB); - MIB.addReg(0); // No write back. bool NumRegs = false; for (unsigned i = CSI.size(); i != 0; --i) { -- cgit v1.2.3