From 8d24618975c6e633b00189e1aa990f6763a3c1cd Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 14 Dec 2011 19:35:22 +0000 Subject: ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579 --- llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp') diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 827883dd49c..662097aee4a 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -1045,3 +1045,13 @@ void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}"; } + +void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " + << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; +} + -- cgit v1.2.3