From 6679fc1a791ed1f673be9143ed5a07755ae80767 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Fri, 5 Jun 2015 18:01:28 +0000 Subject: Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM." as it caused miscompilations and assertion failures (PR23768, http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150601/280380.html). llvm-svn: 239169 --- llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) (limited to 'llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp') diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 188410a5123..f88ac30a91a 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -744,21 +744,10 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { O << "{"; - - // The backend may have given us a register list in non-ascending order. Sort - // it now. - std::vector RegOps(MI->size() - OpNum); - std::copy(MI->begin() + OpNum, MI->end(), RegOps.begin()); - std::sort(RegOps.begin(), RegOps.end(), - [this](const MCOperand &O1, const MCOperand &O2) -> bool { - return MRI.getEncodingValue(O1.getReg()) < - MRI.getEncodingValue(O2.getReg()); - }); - - for (unsigned i = 0, e = RegOps.size(); i != e; ++i) { - if (i != 0) + for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { + if (i != OpNum) O << ", "; - printRegName(O, RegOps[i].getReg()); + printRegName(O, MI->getOperand(i).getReg()); } O << "}"; } -- cgit v1.2.3