From 9da60e016b51d02135a0ea63fc15b4c218c83400 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Tue, 5 Apr 2011 22:18:07 +0000 Subject: ARM disassembler was erroneously accepting an invalid RSC instruction. Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945 --- llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp') diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 786e001127f..db76c11b7b7 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1072,6 +1072,12 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, if (slice(insn, 7, 7)) return false; + // A8.6.3 ADC (register-shifted register) + // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + if (decodeRd(insn) == 15 || decodeRn(insn) == 15 || + decodeRm(insn) == 15 || decodeRs(insn) == 15) + return false; + // Register-controlled shifts: [Rm, Rs, shift]. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRs(insn)))); -- cgit v1.2.3