From ffb2b347ffbdc667169af4f4627cfdf7d64be6a0 Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Thu, 27 Jun 2019 12:41:07 +0000 Subject: [ARM] Fix handling of zero offsets in LOB instructions. The BF and WLS/WLSTP instructions have various branch-offset fields occupying different positions and lengths in the instruction encoding, and all of them were decoded at disassembly time by the function DecodeBFLabelOffset() which returned SoftFail if the offset was zero. In fact, it's perfectly fine and not even a SoftFail for most of those offset fields to be zero. The only one that can't be zero is the 4-bit field labelled `boff` in the architecture spec, occupying bits {26-23} of the BF instruction family. If that one is zero, the encoding overlaps other instructions (WLS, DLS, LETP, VCTP), so it ought to be a full Fail. Fixed by adding an extra template parameter to DecodeBFLabelOffset which controls whether a zero offset is accepted or rejected. Adjusted existing tests (only in error messages for bad disassemblies); added extra tests to demonstrate zero offsets being accepted in all the right places, and a few demonstrating rejection of zero `boff`. Reviewers: DavidSpickett, ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63864 llvm-svn: 364533 --- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 548fb10fb3f..9fb2fa65fdd 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -488,7 +488,7 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -template +template static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, @@ -5908,13 +5908,13 @@ static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, return S; } -template +template static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - if (Val == 0) - S = MCDisassembler::SoftFail; + if (Val == 0 && !zeroPermitted) + S = MCDisassembler::Fail; uint64_t DecVal; if (isSigned) @@ -5965,8 +5965,8 @@ static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, Inst.addOperand(MCOperand::createReg(ARM::LR)); LLVM_FALLTHROUGH; case ARM::t2LE: - if (!Check(S, DecodeBFLabelOperand(Inst, Imm, Address, - Decoder))) + if (!Check(S, DecodeBFLabelOperand( + Inst, Imm, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::t2WLS: @@ -5978,8 +5978,8 @@ static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, if (!Check(S, DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), Address, Decoder)) || - !Check(S, DecodeBFLabelOperand(Inst, Imm, Address, - Decoder))) + !Check(S, DecodeBFLabelOperand( + Inst, Imm, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::t2DLS: -- cgit v1.2.3