From e5ce56fb950bb27f6934f670b9916a50d2b8cfb2 Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Thu, 27 Jun 2019 12:40:55 +0000 Subject: [ARM] Make coprocessor number restrictions consistent. Different versions of the Arm architecture disallow the use of generic coprocessor instructions like MCR and CDP on different sets of coprocessors. This commit centralises the check of the coprocessor number so that it's consistent between assembly and disassembly, and also updates it for the new restrictions in Arm v8.1-M. New tests added that check all the coprocessor numbers; old tests updated, where they used a number that's now become illegal in the context in question. Reviewers: DavidSpickett, ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63863 llvm-svn: 364532 --- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index c6ae7d26bf9..548fb10fb3f 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4486,14 +4486,7 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, const FeatureBitset &featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); - if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) - return MCDisassembler::Fail; - - // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should - // decode as VFP/MVE instructions. - if (featureBits[ARM::HasV8_1MMainlineOps] && - ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || - (Val & 0xE) == 0xE)) + if (!isValidCoprocessorNumber(Val, featureBits)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(Val)); -- cgit v1.2.3