From 924bcfc92f4b0d1f9a82456b1f88e4dc89a143e3 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 23 Aug 2011 17:51:38 +0000 Subject: Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. llvm-svn: 138341 --- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 5711b69796e..c4b2f613cc7 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2392,9 +2392,15 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = Success; - if (Inst.getOpcode() != ARM::t2PLDs) { - unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + switch (Inst.getOpcode()) { + case ARM::t2PLDs: + case ARM::t2PLDWs: + case ARM::t2PLIs: + break; + default: { + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + } } unsigned Rn = fieldFromInstruction32(Insn, 16, 4); -- cgit v1.2.3