From 9e89d8cc5cd048b5ed2037f472f3d38ce2c8328f Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Wed, 5 Nov 2014 12:06:39 +0000 Subject: [ARM] Honor FeatureD16 in the assembler and disassembler Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341 --- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp') diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index c642fdc24ca..682ab9374f5 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -270,6 +270,9 @@ class ARMAsmParser : public MCTargetAsmParser { bool hasThumb2DSP() const { return STI.getFeatureBits() & ARM::FeatureDSPThumb2; } + bool hasD16() const { + return STI.getFeatureBits() & ARM::FeatureD16; + } void SwitchMode() { uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); @@ -2988,6 +2991,10 @@ int ARMAsmParser::tryParseRegister() { return Entry->getValue(); } + // Some FPUs only have 16 D registers, so D16-D31 are invalid + if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) + return -1; + Parser.Lex(); // Eat identifier token. return RegNum; -- cgit v1.2.3