From f82d4ed771a0d85da4d3c779e58a9be9ded3968f Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Fri, 15 Mar 2019 13:36:37 +0000 Subject: [ARM] Remove EarlyCSE from backend There is an issue with early CSE hitting an assert, so temporarily remove the pass from the Arm backend. Bug: https://bugs.llvm.org/show_bug.cgi?id=41081 Differential Revision: https://reviews.llvm.org/D59410 llvm-svn: 356259 --- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target/ARM/ARMTargetMachine.cpp') diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index bd075cda2e4..d0138274d57 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -403,11 +403,9 @@ void ARMPassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); - // Run the parallel DSP pass and its helpers. - if (getOptLevel() == CodeGenOpt::Aggressive) { - addPass(createEarlyCSEPass()); + // Run the parallel DSP pass. + if (getOptLevel() == CodeGenOpt::Aggressive) addPass(createARMParallelDSPPass()); - } // Match interleaved memory accesses to ldN/stN intrinsics. if (TM->getOptLevel() != CodeGenOpt::None) -- cgit v1.2.3