From 0ed7513c83a545e3787c7b1fcf19b96affa604a3 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Wed, 10 Jan 2018 11:13:31 +0000 Subject: [ARM GlobalISel] Map G_FNEG to the FPR bank llvm-svn: 322169 --- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp') diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index fad0e98285e..fb3553f318d 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -263,7 +263,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_FADD: case G_FSUB: case G_FMUL: - case G_FDIV: { + case G_FDIV: + case G_FNEG: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] -- cgit v1.2.3