From dd96e97317064b21a882f15baf75cb2beb2b2e30 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 15 Nov 2010 03:30:30 +0000 Subject: Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113. llvm-svn: 119109 --- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp') diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index b1367883338..bda92e6e68c 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1380,6 +1380,14 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, return true; } +static MachineMemOperand *CopyMMO(const MachineMemOperand *MMO, + unsigned NewSize, MachineFunction *MF) { + return MF->getMachineMemOperand(MachinePointerInfo(MMO->getValue(), + MMO->getOffset()), + MMO->getFlags(), NewSize, + MMO->getAlignment(), MMO->getTBAAInfo()); +} + bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, SmallVector &Ops, unsigned Base, bool isLd, @@ -1487,6 +1495,11 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, if (!isT2) MIB.addReg(0); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); + + // Copy memoperands bug change size to 8. + for (MachineInstr::mmo_iterator mmo = Op0->memoperands_begin(); + mmo != Op0->memoperands_end(); ++mmo) + MIB.addMemOperand(CopyMMO(*mmo, 8, MF)); ++NumLDRDFormed; } else { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, @@ -1500,6 +1513,10 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, if (!isT2) MIB.addReg(0); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); + // Copy memoperands bug change size to 8. + for (MachineInstr::mmo_iterator mmo = Op0->memoperands_begin(); + mmo != Op0->memoperands_end(); ++mmo) + MIB.addMemOperand(CopyMMO(*mmo, 8, MF)); ++NumSTRDFormed; } MBB->erase(Op0); -- cgit v1.2.3