From 9d8f6f3d9d736b08d85c9aca00cb83d49e810cb8 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Fri, 27 Apr 2012 23:51:33 +0000
Subject: ARM: Tweak tADDrSP definition for consistent operand order.

Make the operand order of the instruction match that of the asm syntax.

llvm-svn: 155747
---
 llvm/lib/Target/ARM/ARMInstrThumb.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'llvm/lib/Target/ARM/ARMInstrThumb.td')

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 6335229d3c2..081c0abd6bd 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -363,8 +363,8 @@ def : tInstAlias<"sub${p} sp, sp, $imm",
                  (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
 
 // ADD <Rm>, sp
-def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
-                  "add", "\t$Rdn, $sp, $Rn", []>,
+def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
+                    "add", "\t$Rdn, $sp, $Rn", []>,
               T1Special<{0,0,?,?}> {
   // A8.6.9 Encoding T1
   bits<4> Rdn;
-- 
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