From e1de9e9c3314ef55944b163040c2436e827c7172 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Thu, 22 Aug 2013 12:19:24 +0000 Subject: [ARM] Constrain some register classes in EmitAtomicBinary64 so that we pass these tests with -verify-machineinstrs. llvm-svn: 189006 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp') diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f22c5b9ca4d..ebfa1b118eb 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6360,6 +6360,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, MRI.constrainRegClass(destlo, &ARM::rGPRRegClass); MRI.constrainRegClass(desthi, &ARM::rGPRRegClass); MRI.constrainRegClass(ptr, &ARM::rGPRRegClass); + MRI.constrainRegClass(vallo, &ARM::rGPRRegClass); + MRI.constrainRegClass(valhi, &ARM::rGPRRegClass); } MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); @@ -6467,6 +6469,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, // Store if (isThumb2) { + MRI.constrainRegClass(StoreLo, &ARM::rGPRRegClass); + MRI.constrainRegClass(StoreHi, &ARM::rGPRRegClass); AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2STREXD), storesuccess) .addReg(StoreLo).addReg(StoreHi).addReg(ptr)); } else { -- cgit v1.2.3