From 95cf661534ff6c24e5dba4d156842a00b6af8499 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 8 Mar 2008 00:58:38 +0000 Subject: Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. llvm-svn: 48042 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp') diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 92ab18d5775..2e7d985bf8e 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -211,6 +211,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); + setOperationAction(ISD::PREFETCH , MVT::Other, Expand); if (!Subtarget->hasV6Ops()) { setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); -- cgit v1.2.3