From 7f3d9e1f36fdfe6de61a3fe58bb6d1fed61adca0 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Mon, 1 Jul 2013 18:37:33 +0000 Subject: Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst") Turns out I'd misread the architecture reference manual and thought that was a load/store-store barrier, when it's not. Thanks for pointing it out Eli! llvm-svn: 185356 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp') diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 370962dfa5d..ff8571ba033 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2557,12 +2557,8 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, DAG.getConstant(0, MVT::i32)); } - ConstantSDNode *OrdN = cast(Op.getOperand(1)); - AtomicOrdering Ord = static_cast(OrdN->getZExtValue()); - unsigned Domain = Ord == Release ? ARM_MB::ISHST : ARM_MB::ISH; - return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), - DAG.getConstant(Domain, MVT::i32)); + DAG.getConstant(ARM_MB::ISH, MVT::i32)); } static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, -- cgit v1.2.3