From f6b00c279a5587a25876752a6ecd8da0bed959dc Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Fri, 2 Aug 2019 10:23:05 +0000 Subject: Fix and test inter-procedural register allocation for ARM - Avoid a crash when IPRA calls ARMFrameLowering::determineCalleeSaves with a null RegScavenger. Simply not updating the register scavenger is fine because IPRA only cares about the SavedRegs vector, the acutal code of the function has already been generated at this point. - Add a new hook to TargetRegisterInfo to get the set of registers which can be clobbered inside a call, even if the compiler can see both sides, by linker-generated code. Differential revision: https://reviews.llvm.org/D64908 llvm-svn: 367669 --- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'llvm/lib/Target/ARM/ARMFrameLowering.cpp') diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 7ae0c6ab3cf..d2a5111a4de 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -2080,9 +2080,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, ExtraCSSpill = true; } } - if (!ExtraCSSpill) { + if (!ExtraCSSpill && RS) { // Reserve a slot closest to SP or frame pointer. - assert(RS && "Register scavenging not provided"); LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n"); const TargetRegisterClass &RC = ARM::GPRRegClass; unsigned Size = TRI->getSpillSize(RC); -- cgit v1.2.3