From 5a7c7154703daeddbe7752116e07bd2114971f43 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 27 Oct 2010 00:19:44 +0000 Subject: Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on rdar://8477752. llvm-svn: 117419 --- llvm/lib/Target/ARM/ARMFastISel.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp') diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 7cf7ec03559..3b72285d312 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -746,7 +746,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, RC = ARM::GPRRegisterClass; break; case MVT::i8: - Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB; + Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12; RC = ARM::GPRRegisterClass; break; case MVT::i32: @@ -774,8 +774,6 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, if (isFloat) Offset /= 4; - // The thumb and floating point instructions both take 2 operands, ARM takes - // another register. AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Base).addImm(Offset)); -- cgit v1.2.3