From bb0547d9c4ee594f5df6d5f46befd841bfbfbc93 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 11 Mar 2011 23:09:50 +0000 Subject: Pseudo-ize VMOVDcc and VMOVScc. llvm-svn: 127506 --- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp') diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index a985152701c..cb2a89d01a7 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -708,6 +708,19 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, switch (Opcode) { default: return false; + case ARM::VMOVScc: + case ARM::VMOVDcc: { + unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), + MI.getOperand(1).getReg()) + .addReg(MI.getOperand(2).getReg(), + getKillRegState(MI.getOperand(2).isKill())) + .addImm(MI.getOperand(3).getImm()) // 'pred' + .addReg(MI.getOperand(4).getReg()); + + MI.eraseFromParent(); + return true; + } case ARM::MOVCCr: { BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr), MI.getOperand(1).getReg()) -- cgit v1.2.3