From 5dde1f39c12b7427a5af592dd5eb5438880fa1b1 Mon Sep 17 00:00:00 2001
From: Arnold Schwaighofer <aschwaighofer@apple.com>
Date: Fri, 5 Apr 2013 04:42:00 +0000
Subject: ARM scheduler model: Swift has varying latencies, uops for simple ALU
 ops

llvm-svn: 178842
---
 llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.h')

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 2698132d2d5..7c107bb4195 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -314,6 +314,10 @@ public:
   bool canCauseFpMLxStall(unsigned Opcode) const {
     return MLxHazardOpcodes.count(Opcode);
   }
+
+  /// Returns true if the instruction has a shift by immediate that can be
+  /// executed in one cycle less.
+  bool isSwiftFastImmShift(const MachineInstr *MI) const;
 };
 
 static inline
-- 
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