From 338de3ee561aeefec99255b8be55907d04a5c47b Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 27 Oct 2010 23:12:14 +0000 Subject: Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505 --- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 79b35ad4b97..8e215921998 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -870,8 +870,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { switch (MI->getOpcode()) { default: llvm_unreachable("Unexpected opcode!"); - case ARM::PICSTR: Opcode = ARM::STR; break; - case ARM::PICSTRB: Opcode = ARM::STRB; break; + case ARM::PICSTR: Opcode = ARM::STRrs; break; + case ARM::PICSTRB: Opcode = ARM::STRBrs; break; case ARM::PICSTRH: Opcode = ARM::STRH; break; case ARM::PICLDR: Opcode = ARM::LDRrs; break; case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; @@ -1161,10 +1161,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } { MCInst TmpInst; - TmpInst.setOpcode(ARM::STR); + TmpInst.setOpcode(ARM::STRi12); TmpInst.addOperand(MCOperand::CreateReg(ValReg)); TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateReg(0)); TmpInst.addOperand(MCOperand::CreateImm(4)); // Predicate. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); -- cgit v1.2.3