From fa48c496e2ccde292b74b5dc45aa29c65e3748be Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Sat, 24 Feb 2018 01:32:32 +0000 Subject: [AMDGPU] Shrinking V_SUBBREV_U32 V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when we try to commute V_SUBB_U32 in order to shrink it we do not then process V_SUBBREV_U32 and it stay VOP3. This is fixed. Differential Revision: https://reviews.llvm.org/D43699 llvm-svn: 326011 --- llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/AMDGPU') diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 41f989ad322..994658dd3f8 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -92,7 +92,8 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, case AMDGPU::V_ADDC_U32_e64: case AMDGPU::V_SUBB_U32_e64: - if (TII->getNamedOperand(MI, AMDGPU::OpName::src1)->isImm()) + case AMDGPU::V_SUBBREV_U32_e64: + if (!isVGPR(TII->getNamedOperand(MI, AMDGPU::OpName::src1), TRI, MRI)) return false; // Additional verification is needed for sdst/src2. return true; -- cgit v1.2.3