From 033f99a2e567f0eebec6faa961025318f1e724f5 Mon Sep 17 00:00:00 2001 From: Tim Renouf Date: Fri, 22 Mar 2019 10:11:21 +0000 Subject: [AMDGPU] Added v5i32 and v5f32 register classes They are not used by anything yet, but a subsequent commit will start using them for image ops that return 5 dwords. Differential Revision: https://reviews.llvm.org/D58903 Change-Id: I63e1904081e39a6d66e4eb96d51df25ad399d271 llvm-svn: 356735 --- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp') diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 3e1cf68e265..b397554e76d 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -822,6 +822,10 @@ unsigned getRegBitWidth(unsigned RCID) { case AMDGPU::SReg_128RegClassID: case AMDGPU::VReg_128RegClassID: return 128; + case AMDGPU::SGPR_160RegClassID: + case AMDGPU::SReg_160RegClassID: + case AMDGPU::VReg_160RegClassID: + return 160; case AMDGPU::SReg_256RegClassID: case AMDGPU::VReg_256RegClassID: return 256; -- cgit v1.2.3