From fd6fd007739c66cf36d1bfe288b4a96f901a32fd Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 25 Feb 2019 19:24:46 +0000
Subject: AMDGPU: Correct definitions for bitset instructions

These really read and write the result register, so these need a tied
input.

llvm-svn: 354809
---
 llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp')

diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 2b1264d6f63..e589f60b583 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -276,7 +276,9 @@ static bool shrinkScalarLogicOp(const GCNSubtarget &ST,
         if (Opc == AMDGPU::S_BITSET0_B32 ||
             Opc == AMDGPU::S_BITSET1_B32) {
           Src0->ChangeToImmediate(NewImm);
-          MI.RemoveOperand(2);
+          // Remove the immediate and add the tied input.
+          MI.getOperand(2).ChangeToRegister(Dest->getReg(), false);
+          MI.tieOperands(0, 2);
         } else {
           SrcImm->setImm(NewImm);
         }
-- 
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