From eea72ccbf2d8379a04b7783bc6a72a69ad5dface Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 29 Aug 2015 01:58:21 +0000 Subject: AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates Summary: We were assuming tha if the use operand had a sub-register that the immediate was 64-bits, but this was breaking the case of folding a 64-bit immediate into another 64-bit instruction. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12255 llvm-svn: 246354 --- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/AMDGPU/SIFoldOperands.cpp') diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 5609f3ce2f2..eff9c072f40 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -211,8 +211,12 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI, Imm = APInt(64, OpToFold.getImm()); + const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode()); + const TargetRegisterClass *FoldRC = + TRI.getRegClass(FoldDesc.OpInfo[0].RegClass); + // Split 64-bit constants into 32-bits for folding. - if (UseOp.getSubReg()) { + if (FoldRC->getSize() == 8 && UseOp.getSubReg()) { if (UseRC->getSize() != 8) return; -- cgit v1.2.3