From 1c1aab99aeb8170471589538e8faa1bc39e379e2 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 2 Mar 2018 16:55:33 +0000 Subject: AMDGPU/GlobalISel: InstrMapping for G_TRUNC llvm-svn: 326588 --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp') diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 3cafc0aa7d8..92a9a3a1783 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -314,6 +314,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); break; } + case AMDGPU::G_TRUNC: { + unsigned Dst = MI.getOperand(0).getReg(); + unsigned Src = MI.getOperand(1).getReg(); + unsigned Bank = getRegBankID(Src, MRI, *TRI); + unsigned DstSize = getSizeInBits(Dst, MRI, *TRI); + unsigned SrcSize = getSizeInBits(Src, MRI, *TRI); + OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); + OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); + break; + } case AMDGPU::G_FCMP: { unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI); -- cgit v1.2.3