From 1bab191f25ac74f43a7c25c9a04beb029d843af0 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 5 Oct 2015 13:42:31 +0000 Subject: [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for "msr pan, #imm", while only 1-bit immediate values should be valid. Changed encoding and decoding for msr pstate instructions. Differential Revision: http://reviews.llvm.org/D13011 llvm-svn: 249313 --- llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp') diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index db9fb0e775d..00e0eef266a 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1516,6 +1516,9 @@ static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, uint64_t pstate_field = (op1 << 3) | op2; + if (pstate_field == AArch64PState::PAN && crm > 1) + return Fail; + Inst.addOperand(MCOperand::createImm(pstate_field)); Inst.addOperand(MCOperand::createImm(crm)); -- cgit v1.2.3