From 1f5d9941192d9a5876c44d6c274b4447b9bf2099 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Wed, 25 Apr 2018 14:43:59 +0000 Subject: [AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic. rdar://38674040 llvm-svn: 330831 --- llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp') diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 309f6128e5b..4124302e8ab 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1466,6 +1466,15 @@ bool AArch64InstructionSelector::select(MachineInstr &I, case TargetOpcode::G_VASTART: return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI) : selectVaStartAAPCS(I, MF, MRI); + case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + if (!I.getOperand(0).isIntrinsicID()) + return false; + if (I.getOperand(0).getIntrinsicID() != Intrinsic::trap) + return false; + BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::BRK)) + .addImm(1); + I.eraseFromParent(); + return true; case TargetOpcode::G_IMPLICIT_DEF: I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); -- cgit v1.2.3