From d4acd7ed1093fdf8d12d218212373c761df682c3 Mon Sep 17 00:00:00 2001 From: Balaram Makam Date: Tue, 5 Jul 2016 20:24:05 +0000 Subject: Revert r259387: "AArch64: Implement missed conditional compare sequences." This reverts commit r259387 because it inserts illegal code after legalization in some backends where i64 OR type is illegal for example. llvm-svn: 274573 --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 47 ++----------------------- 1 file changed, 2 insertions(+), 45 deletions(-) (limited to 'llvm/lib/Target/AArch64/AArch64ISelLowering.cpp') diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index cbdac8998a4..d7d403234dc 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -138,16 +138,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::XOR, MVT::i32, Custom); setOperationAction(ISD::XOR, MVT::i64, Custom); - // Custom lowering hooks are needed for OR - // to fold it into CCMP. - setOperationAction(ISD::OR, MVT::i32, Custom); - setOperationAction(ISD::OR, MVT::i64, Custom); - - // Custom lowering hooks are needed for AND - // to fold it into CCMP. - setOperationAction(ISD::AND, MVT::i32, Custom); - setOperationAction(ISD::AND, MVT::i64, Custom); - // Virtually no operation on f128 is legal, but LLVM can't expand them when // there's a valid register class, so we need custom operations in most cases. setOperationAction(ISD::FABS, MVT::f128, Expand); @@ -1622,27 +1612,6 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, return Cmp; } -// Attempt to form conditional compare sequences for and/or trees -// with setcc leafs. -static SDValue tryLowerToAArch64Cmp(SDValue Op, SelectionDAG &DAG) { - SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); - if ((LHS.getOpcode() != ISD::SETCC) || (RHS.getOpcode() != ISD::SETCC)) - return Op; - - bool CanNegate; - if (!isConjunctionDisjunctionTree(Op, CanNegate)) - return SDValue(); - - EVT VT = Op.getValueType(); - SDLoc DL(Op); - SDValue TVal = DAG.getConstant(1, DL, VT); - SDValue FVal = DAG.getConstant(0, DL, VT); - SDValue CCVal; - SDValue Cmp = getAArch64Cmp(Op, FVal, ISD::SETEQ, CCVal, DAG, DL); - return DAG.getNode(AArch64ISD::CSEL, DL, VT, FVal, TVal, CCVal, Cmp); -} - static std::pair getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) { assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) && @@ -1764,18 +1733,6 @@ SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG, return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first; } -SDValue AArch64TargetLowering::LowerAND(SDValue Op, SelectionDAG &DAG) const { - if (Op.getValueType().isVector()) - return LowerVectorAND(Op, DAG); - return tryLowerToAArch64Cmp(Op, DAG); -} - -SDValue AArch64TargetLowering::LowerOR(SDValue Op, SelectionDAG &DAG) const { - if (Op.getValueType().isVector()) - return LowerVectorOR(Op, DAG); - return tryLowerToAArch64Cmp(Op, DAG); -} - static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) { SDValue Sel = Op.getOperand(0); SDValue Other = Op.getOperand(1); @@ -2429,9 +2386,9 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op, case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); case ISD::AND: - return LowerAND(Op, DAG); + return LowerVectorAND(Op, DAG); case ISD::OR: - return LowerOR(Op, DAG); + return LowerVectorOR(Op, DAG); case ISD::XOR: return LowerXOR(Op, DAG); case ISD::PREFETCH: -- cgit v1.2.3