From 3e9a5d346828e8310a45d770928d4e51c5b929e4 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Fri, 27 May 2016 11:36:04 +0000 Subject: Apply clang-tidy's misc-static-assert where it makes sense. Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982 --- llvm/lib/Target/AArch64/AArch64FastISel.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target/AArch64/AArch64FastISel.cpp') diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 316c233b3a7..ffe193e9d4c 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -1607,8 +1607,8 @@ unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) { - assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) && - "ISD nodes are not consecutive!"); + static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR), + "ISD nodes are not consecutive!"); static const unsigned OpcTable[3][2] = { { AArch64::ANDWri, AArch64::ANDXri }, { AArch64::ORRWri, AArch64::ORRXri }, @@ -1654,8 +1654,8 @@ unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) { - assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) && - "ISD nodes are not consecutive!"); + static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR), + "ISD nodes are not consecutive!"); static const unsigned OpcTable[3][2] = { { AArch64::ANDWrs, AArch64::ANDXrs }, { AArch64::ORRWrs, AArch64::ORRXrs }, -- cgit v1.2.3