From 5fb34b5498f3349fb7cbe9039e35eb2fd635ff59 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Tue, 27 Nov 2018 18:05:00 +0000
Subject: [X86] Add cascade lake arch in X86 target.

This is skylake-avx512 with the addition of avx512vnni ISA.

Patch by Jianping Chen

Differential Revision: https://reviews.llvm.org/D54785

llvm-svn: 347681
---
 llvm/lib/Support/Host.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'llvm/lib/Support/Host.cpp')

diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index 9f5bf1ffa12..d5a688c7fb9 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -702,6 +702,12 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
         break;
       }
 
+      if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
+        *Type = X86::INTEL_COREI7;
+        *Subtype = X86::INTEL_COREI7_CASCADELAKE;
+        break;
+      }
+
       if (Features & (1 << X86::FEATURE_AVX512VL)) {
         *Type = X86::INTEL_COREI7;
         *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
-- 
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