From ddf5e86c222c6b5226be53e1250421fe608bb4d0 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Tue, 17 Sep 2019 21:42:38 +0000 Subject: [ARM] VFPv2 only supports 16 D registers. r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 llvm-svn: 372186 --- llvm/lib/Object/ELFObjectFile.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/lib/Object/ELFObjectFile.cpp') diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index a10c643b3b9..bf6ffd6c37b 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -203,7 +203,7 @@ SubtargetFeatures ELFObjectFileBase::getARMFeatures() const { default: break; case ARMBuildAttrs::Not_Allowed: - Features.AddFeature("vfp2d16sp", false); + Features.AddFeature("vfp2sp", false); Features.AddFeature("vfp3d16sp", false); Features.AddFeature("vfp4d16sp", false); break; -- cgit v1.2.3