From f305ead1cce10fd3f82dbf46cd956d4551711b0d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 30 Sep 2009 08:49:50 +0000 Subject: Add a target hook to add pre- post-regalloc scheduling passes. llvm-svn: 83144 --- llvm/lib/CodeGen/LLVMTargetMachine.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index a38d8ccab78..4e713a6ed31 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -317,6 +317,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, PM.add(createPrologEpilogCodeInserter()); printAndVerify(PM); + // Run pre-sched2 passes. + if (addPreSched2(PM, OptLevel)) + printAndVerify(PM); + // Second pass scheduler. if (OptLevel != CodeGenOpt::None) { PM.add(createPostRAScheduler()); -- cgit v1.2.3