From da103bf9ecfcdeb4292b2920c908a416a8b105b4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 14 Dec 2011 20:00:08 +0000 Subject: Model ARM predicated write as read-mod-write. e.g. r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583 --- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 47c533932d6..4418f4023a3 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -281,8 +281,8 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) { if (Kind == SDep::Anti) DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg)); else { - unsigned AOLat = TII->getOutputLatency(InstrItins, MI, - DefSU->getInstr(), Reg); + unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j, + DefSU->getInstr()); DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg)); } } -- cgit v1.2.3