From 9faa09b21e15fdb548abc26cb561d0773fc19798 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 23 Nov 2017 12:44:20 +0000 Subject: [ARM GlobalISel] Support G_FMUL for s32 and s64 TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910 --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index d94ad0d8f3b..c54c715dc73 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -94,6 +94,9 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { case TargetOpcode::G_FSUB: assert((Size == 32 || Size == 64) && "Unsupported size"); return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32; + case TargetOpcode::G_FMUL: + assert((Size == 32 || Size == 64) && "Unsupported size"); + return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32; case TargetOpcode::G_FREM: return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32; case TargetOpcode::G_FPOW: @@ -150,6 +153,7 @@ LegalizerHelper::libcall(MachineInstr &MI) { } case TargetOpcode::G_FADD: case TargetOpcode::G_FSUB: + case TargetOpcode::G_FMUL: case TargetOpcode::G_FPOW: case TargetOpcode::G_FREM: { Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx); -- cgit v1.2.3