From 984997b3a04aff3ebc2b9dc4b0902b64584c7448 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 15 May 2012 23:31:35 +0000 Subject: Enable sub-sub-register copy coalescing. It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. llvm-svn: 156878 --- llvm/lib/CodeGen/RegisterCoalescer.cpp | 9 --------- 1 file changed, 9 deletions(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 11ba9ac2bd1..6770c82af3b 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -278,15 +278,6 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) { SrcIdx, DstIdx); if (!NewRC) return false; - - // We cannot handle the case where both Src and Dst would be a - // sub-register. Yet. - if (SrcIdx && DstIdx) { - DEBUG(dbgs() << "\tCannot handle " << NewRC->getName() - << " with subregs " << TRI.getSubRegIndexName(SrcIdx) - << " and " << TRI.getSubRegIndexName(DstIdx) << '\n'); - return false; - } } else if (DstSub) { // SrcReg will be merged with a sub-register of DstReg. SrcIdx = DstSub; -- cgit v1.2.3