From 7aaa0aa7a70fbacf0c5b5613f4eb2caafc6fbf3d Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Sun, 18 Sep 2011 10:29:29 +0000 Subject: white space cleanups llvm-svn: 139994 --- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'llvm/lib/CodeGen') diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 7c59c7eb5a0..80b4c6053a6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -61,8 +61,8 @@ class VectorLegalizer { // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if // SINT_TO_FLOAT and SHR on vectors isn't legal. SDValue ExpandUINT_TO_FLOAT(SDValue Op); - // Implement vselect in terms of XOR, AND,OR when blend is not supported - // by the target. + // Implement vselect in terms of XOR, AND, OR when blend is not supported + // by the target. SDValue ExpandVSELECT(SDValue Op); SDValue ExpandFNEG(SDValue Op); // Implements vector promotion; this is essentially just bitcasting the @@ -277,9 +277,8 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { // AND,OR,XOR, we will have to scalarize the op. if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) || !TLI.isOperationLegalOrCustom(ISD::XOR, VT) || - !TLI.isOperationLegalOrCustom(ISD::OR, VT)) { - return DAG.UnrollVectorOp(Op.getNode()); - } + !TLI.isOperationLegalOrCustom(ISD::OR, VT)) + return DAG.UnrollVectorOp(Op.getNode()); assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size"); // Bitcast the operands to be the same type as the mask. -- cgit v1.2.3